The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device, for which a fault diagnosis can be readily made, and a method of diagnosing the same.
In an integrated circuit device including logic circuits, it is judged whether various elements have desired functions and performance or not, by applying an input signal indicative of a test pattern to the integrated circuit device. Such judgment is generally called "diagnosis". In making a diagnosis, it is required to use a series of input signals capable of diagnosing almost all of the elements included in the integrated circuit. A ratio of the number of diagnosable elements to the total number of elements included in the integrated circuit is defined as the rate of diagnosis. Accordingly, it is required for a series of input signals to be able to obtain a practically satisfactory rate of diagnosis by the smallest possible numbers of steps. For an ordinary integrated circuit device, thousands of steps are required to obtain a satisfactory rate of diagnosis.
The above-mentioned series of input signals has hitherto been produced manually, and therefore a large amount of work is required. Specifically, for a gate array integrated circuit device whose design work is automated for the most part and whose design period is shortened to about one month, a ratio of a period for producing a series of input signals for diagnostic use to the design period is inevitably increased. This is the most serious obstacle to the shortening of development period.
Further, it has been proposed and tried to automatically produce a series of input signals by means of an electronic computer. In many cases, however, a satisfactory rate of diagnosis is not obtained unless certain restrictions are imposed on logical construction.
As described in a Japanese patent application specification (Laid-open No. 133644/1982), the following methods have been used to solve the above-mentioned problems. In one of the methods, that is, in the scanin scan-out method, flip-flops included in an integrated circuit are connected in series to form a shift register, an input signal is applied to the integrated circuit through the shift register to operate the integrated circuit, and the result of the operation is delivered to the outside through the shift register. In the other method, a shift register for diagnostic use only is provided on a semiconductor substrate at a peripheral portion thereof, desired parts of an integrated circuit which is formed on the semiconductor substrate in accordance with a master slice method, are connected to bits of the shift register by wiring, and the outputs from the desired parts are applied to the shift register in parallel, and then taken out of the shift register in series with the aid of a shift clock.
In these conventional methods, it is possible to diagnose a plurality of combinational logic circuits, but it is impossible to diagnose individual combinational logic circuits. Therefore, the rate of diagnosis is decreased.
Further, a Japanese patent application specification (Laid-open No. 87142/1979) shows a structure in which flip-flops can operate in an ordinary mode and moreover can be accessed directly through selection of select wiring in a diagnostic mode. In this structure, however, only the flip-flops are diagnosed, and it is impossible to diagnose a logic circuit including a combinational circuit.
Furthermore, a Japanese patent application specification (Laid-open No. 93430/1981) discloses that a given one selected from flip-flops is caused to perform a latch operation, and the remaining flip-flops are converted into combinational circuits. In such a prior art, however, only the flip-flops are diagnosed, and it is impossible to diagnose a circuit part including a combinational circuit.